The present invention generally relates to multi-core processor systems, and, more particularly, to a system and a method for dynamically migrating stash transactions in multi-core processor systems used in a computer network.
Multi-core processor systems include one or more central processing units (CPUs), each of which may have multiple processor cores. The multiple cores of the CPUs use shared memory and input/output resources for processing data. Multi-core processor systems are known for high processing speeds that render them useful for data intensive applications. By virtue of their multi-core architecture, the CPUs can execute several instructions simultaneously, which considerably increases processing speed. This processing speed can be further increased by stashing, which entails use of a cache memory. The cache memory is a small, but fast local memory having limited storage capacity. Since cache access times are less than those of main memories, frequently accessed data is stored in the cache memory, which reduces processing time and latency associated with instructions that require loading/storing of data.
The multi-core processor systems by virtue of their processing prowess are used as servers in computer networks such as Ethernet local area networks (LANs). The CPUs of these multi-core processor systems used as servers process packets received from input/output (I/O) devices. The packets are stored in a buffer. An input output memory management unit (IOMMU) assigns a stash transaction destination identification (ID) to each packet based on the packet originating I/O device. The stash transaction destination ID includes a cache register ID of a processor core associated with the packet originating I/O device. Stash transactions are then initiated and the packets are broadcast to the various processor cores for processing. Stashing the packets in the respective cache memories of the processor cores ensures faster accesses times and thus reduced latency.
The multiple processor cores simultaneously execute different packets as threads. To efficiently manage power in the above setting, an operating system (OS) scheduler is used. The OS scheduler migrates, i.e., schedules-in and schedules-out, the threads from one core to another. The thread migration is performed in a manner that prevents any of the cores from being overloaded.
Thread migration is also essential for ensuring power efficiency in a multi-core processor system. If the multi-core processor system is under-utilized, the OS scheduler may choose to migrate threads to a single processor core and power-down the other processor cores. This will reduce power consumption. However, thread migration is challenging in systems that intend to benefit from stashing. Since the processor core to which a stash transaction will be directed is fixed at I/O device initialization, thread migration at a later stage of processing becomes cumbersome. This inflexibility may prevent the OS scheduler from effectively managing power and balancing load across the processor cores. Further, a processor core that executes the thread after thread migration has to access cache data related to the thread from a processor core that previously executed the thread. However, due to the aforementioned disadvantages, a read-miss occurs on the cache data and the processor core that executes the thread after thread migration has to access the cache data from the processor core that previously executed the thread by performing a snooping operation. The snooping operation increases the thread execution time since the processor core halts instructions that are in the pipeline until the cache data has been retrieved from the processor core that previously executed the thread. Hence, the overall system performance decreases.
Therefore, it would be advantageous to have a system and method that enables dynamic migration of stash transactions without snooping of cache data, and enables thread migration.